1. Field of the present invention
The present disclosure relates to substrate storing methods and substrate processing apparatuses.
2. Description of the Related Art
There exists a FOUP (Front Opening Unified Pod) for storing and conveying a plurality of wafers. The FOUP is disposed at a load port (LP) provided in a substrate processing apparatus. Wafers in the FOUP are carried at a certain timing and processed in a processing chamber of the substrate processing apparatus. Then, the wafers are returned to the FOUP. If a processed wafer is returned to the FOUP before all of unprocessed wafers have been carried outside the FOUP, the processed wafer may be mixed with the unprocessed wafers. Therefore, defects may be found in devices formed on the wafers, or characteristics of the devices may vary.
In Patent Document 1, a method is proposed, in which the processed wafer is temporarily retracted to a storage area so as to avoid mixture of the unprocessed substrate and the processed substrate. In patent document 1, the processed wafer is returned from the storage area to the FOUP at timing when all of the unprocessed wafers are carried outside the FOUP. Also, in Patent Document 2, a method of N2 purging is disclosed, in which gas in the FOUP on the load port is replaced by N2 gas, thereby improving an atmosphere in the FOUP.
However, the storage area is a temporary space for storing the wafers. Therefore, service life of the device (hereinafter referred to as service life of wafer) formed on the wafer is reduced as a time during which the processed wafer is kept in the storage area becomes longer because defects or change of characteristics of the device may occur. For example, the replacement of gas by the N2 purging can be performed more locally in the FOUP in comparison to the storage area. Thus, effectiveness of N2 purging becomes greater in the FOUP than in the storage area. Hence, preferably, the time during which the wafer is kept in the storage area is reduced and the processed wafer is returned to the FOUP on the load port as soon as possible, in order to avoid the occurrence of defects, etc., in the wafer.
[Patent Document 1]: Japanese Laid-open Patent Publication No. 2010-251655
[Patent Document 2]: Japanese Laid-open Patent Publication No. 2013-179287